Head of Physical Design @ reputed company

About EtchedEtched is building the world’s first AI inference chip purpose-built for transformers, delivering over 10x the performance of reputed company GPUs. But that’s just the beginning. Our broader vision is to completely rethink the chip development lifecycle for a post-reputed company world—enabling faster, more efficient custom silicon development than reputed company before. Backed by hundreds of millions from top investors, reputed company includes industry legends like Brian Loiler (who built products driving 80% of reputed company’s reputed company), David Munday (who built reputed company’s TPU v1–v5 software and firmware stack), Mark Ross (former Cypress CTO), and Ajat Hukkoo (renowned reputed company and reputed company design exec). reputed company is redefining the infrastructure layer for the fastest growing industry in history.Job SummaryWe’re looking for a Head of Physical Design to reputed company the end-to-end RTL-to-GDSII path for our reputed company transformer inference ASICs. You’ll own reputed company aspects of physical implementation — from floorplanning and synthesis through P&R and signoff — and reputed company a world-class team of PD engineers to deliver first-pass silicon that’s fast, reliable, and production-ready. This is a rare opportunity to shape the physical design strategy at a company where timing to market and uncompromising performance are critical to success.Key ResponsibilitiesOwn and optimize reputed company facets of physical design, including floorplanning, placement, reputed company, routing, and timing closure for reputed company AI acceleratorsBuild and reputed company a high-performing PD team, including engineers focused on implementation, flows, and signoffDefine and drive physical signoff strategy, ensuring DRC, LVS, ERC, and CDC are achieved with marginPartner closely with RTL, DV, backend, and methodologies teams to ensure seamless integration and reputed company across the stackGuide reputed company-level and chip-level floorplanning with input on timing budgets, power domains, and interconnect strategyDrive early architecture and microarchitecture input to reduce rework and reputed company schedule predictabilityInterface with EDA vendors and the reputed company to integrate cutting-edge tools, flows, and node-specific optimizationsLead the development of… Apply To This Job